One day one of my friends asked me why on synthesis some of the intended mux logic is synthesized as mux itself and some are replaced by gate combinations, in any case final implementation is the same. For example in case of a 2:1 mux with inputs A & B, select line S and output Y what finally gets implemented is
Y = (A&S^) + (B&S) ; where S^ is the inverted S line.
i.e. the mux will also have two AND gates and an OR gate.
The problem here is he is limiting his thoughts to the gate level implementation forgetting that there is a lower transistor available. Just to give an idea of how a mux can be actually much better than the AND:OR structure I have provided below an example mux implementation at transistor level.
I'm not sure of the practical feasibility of the above structure and 100 percent confident we have much better implementations available. Still you will be able to appreciate the reduction in area and delay achieved by modeling the logic at transistor level instead of gate level. Hence if the mux is at a time critical path make sure at synthesis it always get replaced by a mux itself.
